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Preliminary W49F201 128K x 16 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F201 is a 2-megabit, 5-volt only CMOS flash memory organized as 128K x 16 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F201 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
*
Single 5-volt operations: - 5-volt Read/Erase/Program Fast Program operation: - Word-by-Word programming: 50 S (max.) Fast Erase operation: 60 mS (typ.) Fast Read access time: 45/55 nS Endurance: 1K/10K cycles (typ.) Ten-year data retention Hardware data protection Sector configuration - One 8K words boot block with lockout protection - Two 8K words parameter blocks - One 104K words (208K bytes) Main Memory Array Blocks
*
Low power consumption - Active current: 25 mA (typ.) - Standby current: 20 A (typ.)
*
* *
* * * * * *
Automatic program and erase timing with internal VPP generation End of program or erase detection - Toggle bit - Data polling
* * * *
Latched address and data TTL compatible I/O JEDEC standard word-wide pinouts Available packages: 44-pin SOP, 48-pin TSOP
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Publication Release Date: June 1999 Revision A1
Preliminary W49F201
PIN CONFIGURATIONS BLOCK DIAGRAM
VDD VSS
NC NC NC A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
44-pin SOP
RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 NC GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
CE OE WE RESET CONTROL OUTPUT BUFFER
DQ0
. .
DQ15
A0
. .
A16
DECODER
1FFFF MAIN MEMORY 104K WORDS 06000 05FFF PARAMETER BLOCK2 8K WORDS 04000 03FFF PARAMETER BLOCK1 8K WORDS 02000 BOOT BLOCK 01FFF 8K WORDS 00000
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC NC NC NC A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 7 46 45 44 43 42 41
48-pin TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 NC GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE GND CE A0
PIN DESCRIPTION SYMBOL
RESET A0-A16 DQ0-DQ15 CE OE WE VDD GND NC Reset Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection
PIN NAME
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Preliminary W49F201
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49F201 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data to the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details.
Reset Operation
The RESET input pin can be used in some application. When RESET pin is at high state, the device is in normal operation mode. When RESET pin is driven low for at least a period of TRP, it will halts the device and all outputs are at high impedance state. The device also resets the internal state machine to read array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to assure data integrity. As the high state re-asserted to the RESET pin, the device will return to read or standby mode, it depends on the control signals. The system can read data TRH after the RESET pin returns to VIH. The other function for RESET pin is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be reprogrammed even though the boot block lockout function is enabled.
Boot Block Operation
There is one 8K-word boot block in this device, which can be used to store boot code. It is located in the first 8K words of the memory with the address range from 0000(hex) to 1FFF(hex). See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. There is one condition that the lockout feature can be overrides. Just apply 12V to RESET pin, the lockout feature will temporary be inactivated and the boot block can be erased/programmed. Once the RESET pin returns to TTL level, the lockout feature will be activated again. In order to detect whether the boot block feature is set on the 8K-words block, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the output data in DQ0 is "0", the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be Publication Release Date: June 1999 Revision A1
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Preliminary W49F201
completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. The entire memory array will be erased to FF(hex). by the chip erase operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the chip erase function will erase all the sectors except the boot mode.
Sector Erase Operation
The three sectors, main memory and two parameters blocks, can be erased individually by initiating a six-word command sequence. Sector address is latched on the falling WE edge of the sixth cycle while the 30(hex) data input command is latched at the rising edge of WE. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. When the boot block lockout feature is inactivated, the boot block and the main memory block will be erased together. Once the boot block is locked, only the main memory block will be erased by the execution of sector erase operation.
Program Operation
The W49F201 is programmed on a word-by-word basis. Program operation can only change logical data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot block from "0" to "1" is needed before programming. The program operation is initiated by a 4-word command cycle (see Command Codes for Word Programming). The device will internally enter the program operation immediately after the wordprogram command is entered. The internal program timer will automatically time-out (50 S max. TBP) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F201 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V typical. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49F201 includes a data polling feature to indicate the end of a program or erase cycle. When the W49F201 is in the internal program or erase cycle, any attempt to read DQ7 of the last word loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed.
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Preliminary W49F201
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49F201 provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code, 00DA(hex). A read from address 0001(hex) outputs the device code, 00AE(hex). The product ID operation can be terminated by a three-word command sequence or an alternative one-word command sequence (see Command Definition table). In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts.
TABLE OF OPERATING MODES
Operating Mode Selection
(VHH = 12V 5 %)
MODE CE Read Erase/Program Standby Erase/Program Inhibit Output Disable Product ID VIL VIL VIH X X X VIL VIL Reset X OE VIL VIH X VIL X VIH VIL VIL X WE VIH VIL X X VIH X VIH VIH X
RESET
PINS ADDRESS AIN AIN X X X X A0 = VIL; A1-A15 = VIL; A9 = VHH A0 = VIH; A1-A15 = VIL; A9 = VHH X Dout Din High Z High Z/DOUT High Z/DOUT High Z Manufacturer Code 00DA (Hex) Device Code 00AE (Hex) High Z DQ.
VIH VIH VIH VIH VIH VIH VIH VIH VIL
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Preliminary W49F201
TABLE OF COMMAND DEFINITION
COMMAND DESCRIPTION
NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read Chip Erase Main Memory Erase Word Program Boot Block Lockout Product ID Entry Product ID Exit (1) Product ID Exit (1)
Notes:
1 6 6 4 6 3 3 1
AIN
DOUT 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 5555 80 5555 80 5555 A0 5555 80 5555 90 5555 F0 5555 AA 5555 AA AIN DIN 2AAA 55 5555 40 5555 AA 2AAA 55 2AAA 55 5555 10 SA 30
5555 AA 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA XXXX F0
1. Address Format: A14-A0 (Hex); Data Format: DQ15-DQ8 (Don't Care); DQ7-DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. SA: Sector Address SA = 03XXXh for Parameter Block1 SA = 05XXXh for Parameter Block2 SA = 1FXXXh - for Main Memory Block when Boot Block lockout feature is activated - for both Boot Block and Main Memory Block when Boot Block lockout feature is inactivated
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Preliminary W49F201
Command Codes for Word Program
WORD SEQUENCE 0 Write 1 Write 2 Write 3 Write ADDRESS 5555H 2AAAH 5555H Programmed-address Pause 50 S DATA AAH 55H A0H Programmed-data
Word Program Flow Chart Word Program Command Flow
Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555
Load data Din to programmedaddress
Pause 50 S
Exit
Notes for software program code: Data Format: DQ15-DQ8: Don't Care; DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) *It is not allowed to assert read command during the 4-word command sequence(program). To assert the read command during the 4-word command sequence will abort programming procedure.
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Publication Release Date: June 1999 Revision A1
Preliminary W49F201
Command Codes for Chip Erase
BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 200 mS DATA AAH 55H 80H AAH 55H 10H
Chip Erase Acquisition Flow
Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555
Pause 200 mS
Exit
Notes for chip erase: Data Format: DQ15-DQ8: Don't Care; DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex)
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Preliminary W49F201
Command Codes for Sector Erase
BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH SA* Pause 200 mS DATA AAH 55H 80H AAH 55H 30H
Sector Erase Acquisition Flow
Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address SA*
Pause 200 mS
Exit
Notes for chip erase: Data Format: DQ15-DQ8: Don't Care; DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) SA = 03XXX for parameter block1 SA = 05XXX for parameter block2 SA = 1FXXX - for Main Memory Block when Boot Block lockout feature is activated - for both Boot Block and Main Memory Block when Boot Block lockout feature is inactivated
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Publication Release Date: June 1999 Revision A1
Preliminary W49F201
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE SEQUENCE ALTERNATE PRODUCT (6) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 1 Write 2 Write 3 Write 5555 2AAA 5555 Pause 10 S DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT (7) ADDRESS 5555H 2AAAH 5555H Pause 10 S DATA AAH 55H F0H
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product Identification Entry (1)
Load data AA to address 5555
Product Identification and Boot Block Lockout Detection Mode (3)
Product Identification Exit(7)
Load data AA to address 5555 (2)
Load data 55 to address 2AAA
Read address = 0000 data = 00DA
Load data 55 to address 2AAA
Load data 90 to address 5555
Read address = 0001 data = 00AE
(2)
Load data F0 to address 5555
Pause 10 S
(4)
Read address = 0002 data in DQ0 =1/0
Pause 10 S
(5) Normal Mode
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ15-DQ8 (Don't Care), DQ7-DQ0 (Hex); Address Format: A14-A0 (Hex) (2) A1-A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0 = 1, the boot block programming lockout feature is activated; if the output data in DQ0 = 0, the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
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Preliminary W49F201
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write BOOT BLOCK LOCKOUT FEATURE SET ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 200 mS DATA AAH 55H 80H AAH 55H 40H
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout Feature Set Flow
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 80 to address 5555
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 40 to address 5555
Pause 200 mS
Exit
Notes for boot block lockout enable: Data Format: DQ15-DQ8 Don't Care), DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex)
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Publication Release Date: June 1999 Revision A1
Preliminary W49F201
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential except OE Transient Voltage (<20 nS ) on Any Pin to Ground Potential Voltage on OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V C C V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC Operating Characteristics
(VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS MIN. TYP. MAX. 50
UNIT
Power Supply Current Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
ICC
CE = OE = VIL, WE = VIH, all DQs open Address inputs = VIL/VIH, at f = 5 MHz
-
25
mA
ISB1
CE = VIH, all DQs open Other inputs = VIL/VIH
-
2
3
mA
ISB2
CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V/GND
-
20
100
A
ILI ILO VIL VIH VOL VOH
VIN = GND to VDD VOUT = GND to VDD IOL = 2.1 mA IOH = -0.4 mA
-0.3 2.0 2.4
-
10 10 0.8 VDD +0.5 0.45 -
A A V V V V
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Publication Release Date: June 1999 Revision A1
Preliminary W49F201
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS
CAPACITANCE
(VDD = 5.0V, TA = 25 C, f = 1 MHz)
PARAMETER I/O Pin Capacitance Input Capacitance
SYMBOL CI/O CIN
CONDITIONS VI/O = 0V VIN = 0V
MAX. 12 6
UNIT pf pf
AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load CONDITIONS 0V to 3.0V < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF
AC Test Load and Waveform
+5V
1.8K
D OUT
30 pF (Including Jig and Scope)
1.3K
Input
3V 1.5V 0V Test Point
Output
1.5V
Test Point
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Preliminary W49F201
AC Characteristics, continued
Read Cycle Timing Parameters
(VCC = 5.0V 10 %, VCC = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
W49F201-45 MIN. MAX. 45 45 35 25 25 -
W49F201-55 MIN. 55 0 0 0 MAX. 55 55 40 25 25 -
UNIT
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time
CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output
TRC TCE TAA TOE TCLZ TOLZ TCHZ TOHZ TOH
45 0 0 0
nS nS nS nS nS nS nS nS nS
Output Hold from Address Change
Note: The parameter of TCLZ, TOLZ, TCHZ, TOHZ are characterized only and is not 100% tested.
Write Cycle Timing Parameters
PARAMETER Address Setup Time Address Hold Time
WE and CE Setup Time WE and CE Hold Time OE High Setup Time OE High Hold Time CE Pulse Width WE Pulse Width WE High Width
SYMBOL TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBC TEC
MIN. 0 50 0 0 0 0 70 70 100 50 10 -
TYP. 35 60
MAX. 50 200
UNIT nS nS nS nS nS nS nS nS nS nS nS S mS
Data Setup Time Data Hold Time Word programming Time Erase Cycle Time
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
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Preliminary W49F201
AC Characteristics, continued
Data Polling and Toggle Bit Timing Parameters
PARAMETER SYM. W49F201-45 MIN. OE to Data Polling Output Delay CE to Data Polling Output Delay
WE High to OE Low for Data Polling
W49F201-55 MIN. 100 100 MAX. 40 55 40 55 -
UNIT
MAX. 35 45 35 45 -
TOEP TCEP TOEHP TOET TCET TOEHT
100 100
nS nS nS nS nS nS
OE to Toggle Bit Output Delay CE to Toggle Bit Output Delay
WE High to OE Low for Toggle Bit
Hardware Reset Timing Parameters
PARAMETER RESET Pulse Width RESET High Time Before Read(1) SYM. TRP TRH MIN. 500 50 MAX. UNIT nS nS
Note: 1. The parameters are characterized only and is not 100% tested.
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Publication Release Date: June 1999 Revision A1
Preliminary W49F201
TIMING WAVEFORMS
Read Cycle Timing Diagram
TRC Address A16-0 TCE CE
OE
TOE
VIH WE
TOLZ
TOHZ
TCLZ High-Z
TOH Data Valid TAA
TCHZ High-Z Data Valid
DQ15-0
WE Controlled Command Write Cycle Timing Diagram
TAS Address A16-0
TAH
CE
TCS TOES
TCH T OEH
OE TWP T WPH
WE
TDS DQ15-0 Data Valid
TDH
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Preliminary W49F201
Timing Waveforms, continued
CE Controlled Command Write Cycle Timing Diagram
TAS
TAH
Address A16-0 TCPH
TCP CE TOES OE WE TDS DQ15-0 High Z Data Valid
TOEH
TDH
Program Cycle Timing Diagram
Word Program Cycle Address A16-0 5555 2AAA 5555 Address
DQ15-0
AA
55
A0
Data-In
CE *
OE * TWP WE Word 0
T WPH
TBP
Word 1
Word 2
Word 3
Internal Write Start
*Note: It is not allowed to assert read operation(CE# &OE# are both active) during the command sequence. If read command is asserted during the command sequence, then the device will return to read mode(abort write).
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Publication Release Date: June 1999 Revision A1
Preliminary W49F201
Timing Waveforms, continued
DATA Polling Timing Diagram
Address A16-0 WE
An
An
An
An
TCEP CE TOEHP OE TOEP DQ7 X X TBP or TEC X X TOES
Toggle Bit Timing Diagram
Address A16-0
WE
CE TOEHT OE TOES
DQ6 TBP or TEC
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Preliminary W49F201
Timing Waveforms, continued
Boot Block Lockout Enable Timing Diagram
Six-word code for Boot Block Lockout Feature Enable Address A16-0 5555 2AAA 5555 5555 2AAA 5555
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX40
CE
OE WE
TWP TWPH SW0 SW1 SW23 SW3 SW4 SW5
TEC
*Note: It is not allowed to assert read operation(CE# &OE# are both active) during the command sequence. If read command is asserted during the command sequence, then the device will return to read mode(abort write).
Chip Erase Timing Diagram
Six-word code for 5V-only software chip erase Address A16-0 5555 2AAA 5555 5555 2AAA 5555
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
CE
OE WE
TWP TWPH SW0 SW1 SW2 SW3 SW4 SW5
TEC
Internal Erase starts
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Publication Release Date: June 1999 Revision A1
Preliminary W49F201
Timing Waveforms, continued
Sector Erase Timing Diagram
Six-word code for 5V-only software Main Memory Erase Address A16-0 5555 2AAA 5555 5555 2AAA SA
DQ15-0 CE
XXAA
XX55
XX80
XXAA
XX55
XX30
OE WE
TWP TWPH SW0 SW1 SW2 SW3 SW4 SW5
TEC
Internal Erase starts
*Note: It is not allowed to assert read operation(CE# &OE# are both active) during the command sequence. If read command is asserted during the 4-word command sequence, then the device will return to read mode(abort write). SA = Sector Address
Reset Timing Diagram
CE
OE TRH RESET
TRP
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Preliminary W49F201
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) W49F201S-45 W49F201S-55 W49F201T-45 W49F201T-55 W49F201S-45B W49F201S-55B W49F201T-45B W49F201T-55B
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
STANDBY VDD CURRENT MAX. (A) 200 (CMOS) 200 (CMOS) 200 (CMOS) 200 (CMOS) 200 (CMOS) 200 (CMOS) 200 (CMOS) 200 (CMOS) 44-pin SOP 44-pin SOP
PACKAGE
CYCLE
45 55 45 55 45 55 45 55
50 50 50 50 50 50 50 50
1K 1K 1K 1K 10K 10K 10K 10K
48-pin TSOP (12 mm x 20 mm) 48-pin TSOP (12 mm x 20 mm) 44-pin SOP 44-pin SOP 48-pin TSOP (12 mm x 20 mm) 48-pin TSOP (12 mm x 20 mm)
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Publication Release Date: June 1999 Revision A1
Preliminary W49F201
PACKAGE DIMENSIONS 48-pin TSOP (12 mm x 20 mm)
1
48
Dimension in mm Symbol
Dimension in Inches MIN. NOM. MAX.
e A A1 E b A2 D HD E b c e L A2 L L1 A1 A Y L1 Y
MIN.
NOM.
MAX.
1.20 0.05 0.95 18.3 19.8 11.9 0.17 0.10 0.50 0.50 0.60 0.80 0.70 0.10 0 5 0 1.00 18.4 20.0 12.0 0.22 1.05 18.5 20.2 12.1 0.27 0.21 0.002
0.047 0.037 0.039 0.041 0.720 0.724 0.728 0.780 0.787 0.795 0.468 0.472 0.476 0.007 0.009 0.011 0.008 0.004 0.020 0.020 0.024 0.028 0.031 0.004 5
c D HD
44-pin SOP
44
23 L L1
Symbol A A1 0.10 2.26 0.36 0.10 13.10 15.80 1.12 0.60 0.41 0.15 13.30 16.00 1.27 0.80 1.35 2.82 0.50 0.21 28.32 13.50 16.20 1.42 1.00 0.10 0 7 0 Dimension in mm MIN. NOM. MAX. 3.00 0.004 0.089 0.014 0.004 1.105 0.516 0.622 0.044 0.024 0.016 0.006 1.110 0.524 0.630 0.050 0.032 0.053 0.004 7 0.111 0.020 0.008 1.115 0.531 0.638 0.056 0.040 Dimension in Inches MIN. NOM. MAX. 0.118
E HE
A2 b c
1
22
c
D E HE e L
28.07 28.19
D A2 A e b A1
L1 Y
Y
SEATING PLANE
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Preliminary W49F201
VERSION HISTORY
VERSION A1 DATE Jun. 1999 PAGE DESCRIPTION Renamed from W29F201C
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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Publication Release Date: June 1999 Revision A1

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